//////////////////////////////////////////////////////////////////////////////////
// INSTITUTION:    Xidian University
// DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
// 
// Create Date:    16:53:58 02/14/2016 
// Design Name:    PWM_VALUE_SET
// Module Name:    PWM_VALUE_SET
// Project Name:   PWM
// Target Devices: EP3C16F484C6
// Tool versions:  Quartus II 13.1
// Design Lauguage:Verilog-HDL
// Dependencies:   -
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: if i_compare_value < i_compare_set_value o_compare_result = 1
//                      otherwise o_compare_result = 0
//
//////////////////////////////////////////////////////////////////////////////////
module PWM_VALUE_SET (
									input 	 		   i_sys_clk,
									input					i_sys_rst,
									input					i_ext_trig,
									output reg	[7:0]	o_compare_set_value
								);

reg r_ext_trig;

assign w_value_set = i_ext_trig & ~r_ext_trig;
					
always @ (posedge i_sys_rst or posedge i_sys_clk)
begin
	if( i_sys_rst )begin
		r_ext_trig <= 1'b0;
	end else begin
		r_ext_trig <= i_ext_trig;
	end	
end					
always @ (posedge i_sys_rst or posedge i_sys_clk)
begin
	if( i_sys_rst )begin
		o_compare_set_value <= 8'd0;
	end else begin
		if( w_value_set )begin
			case( o_compare_set_value )
				8'd0:   begin o_compare_set_value<= 8'd10; end
				8'd10:  begin o_compare_set_value<= 8'd20; end
				8'd20:  begin o_compare_set_value<= 8'd30; end
				8'd30:  begin o_compare_set_value<= 8'd40; end
				8'd40:  begin o_compare_set_value<= 8'd50; end
				8'd50:  begin o_compare_set_value<= 8'd60; end
				8'd60:  begin o_compare_set_value<= 8'd70; end
				8'd70:  begin o_compare_set_value<= 8'd80; end
				8'd80:  begin o_compare_set_value<= 8'd90; end
				8'd90:  begin o_compare_set_value<= 8'd100; end
				8'd100: begin o_compare_set_value<= 8'd0; end 
				default:begin o_compare_set_value<= 8'd0; end
			endcase
		end
	end
end

endmodule
